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The Thevenin equivalent circuit for the network to the left of terminals a; b in Fig. 2-26(a) has VTh RTh 100 2 0:1 cos !t 1 0:05 cos !t 200 100 2 50 200 0:7 0:5 50 0:004 Now by V

Fig. 7-10

Together, the Thevenin equivalent circuit and the diode model form the circuit in Fig. 2-26(c). Ohm s law, VTh VF 1 0:05 cos !t 0:5 5 0:5 cos !t mA RTh RF 50 50 vD VF RF iD 0:5 50 0:005 0:0005 cos !t 0:75 0:025 cos !t iD

The Thevenin equivalent circuit has already been determined in Problem 2.7. By (2.4), the dc load line is given by iD VTh v 1 v D D 20 20vD RTh RTh 50 50 mA 1

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7.24 Express the set of solutions of each inequality below in terms of the notation for intervals: (a) 2x + 3 < 9 (e) 3 < 4x 5 < 7 2x 5 <1 (i) x 2 (b) 5x + 1 6 (f ) 1 2x + 5 < 9 (j) x 2 6 (c) 3x + 4 5 (g) |x + 1| < 2 (k) (x 3)(x + 1) < 0 (d) 7x 2 > 8 (h) |3x 4| 5

In Fig. 2-27, (1) has been superimposed on the diode characteristic, replotted from Fig. 2-26(b). As in Example 2.7, equivalent time scales for vTh and iD are laid out adjacent to the characteristic curve. Since the diode characteristic is linear about the Q point over the range of operation, only dynamic load lines corresponding to the maximum and minimum of vTh need be drawn. Once these two dynamic load lines are constructed parallel to the dc load line, iD can be sketched.

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The Thevenin equivalent circuit of Problem 2.7 is valid here. Moreover, the intersection of the dc load line and the diode characteristic in Fig. 2-27 gives IDQ 5 mA and VDQ 0:75 V. The dynamic resistance is, then, by (2.5), rd vD 0:7 0:5 50 0:004 iD

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We now have all the values needed for analysis using the small-signal circuit of Fig. 2-12. By Ohm s law, vth 0:05 cos !t 0:5 cos !t mA 50 50 RTh rd vd rd id 50 0:0005 cos !t 0:025 cos !t V iD IDQ id 5 0:5 cos !t mA vD VDQ vd 0:75 0:025 cos !t V id

7.25 For what values of x are the graphs of (a) f (x) = (x 1)(x + 2) and (b) f (x) = x(x 1)(x + 2) above the x-axis GC Check your answers by means of a graphing calculator. 7.26 Prove Theorem 7.1. [Hint: Solve f (r) = 0 for a0 .] 7.27 Prove Theorem 7.2. [Hint: Make use of the algebra following Problem 7.21.]

A voltage source, vS 0:4 0:2 sin !t V, is placed directly across a diode characterized by Fig. 2-26(b). The source has no internal impedance and is of proper polarity to forward-bias the diode. (a) Sketch the resulting diode current iD . (b) Determine the value of the quiescent current IDQ .

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