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We replace RL with a driving-point source oriented such that vdp vL . circuited), vgs 0; thus, Ro RD k 1 rds 2
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As every transaction results in an equal amount of debits and credits in the ledger, the total of all debit entries in the ledger should equal the to tal of all credit entries. At the end of the accounting period, we check this equality by preparing a two-column schedule called a trial balance, which compares the total of all debit balances with the total of all credit balances. The procedure is as follows: 1. List account titles in numerical order. 2. Record balances of each account, entering debit balances in the left column and credit balances in the right column. 3. Add the columns and record the totals. 4. Compare the totals. They must be the same. If the totals agree, the trial balance is in balance, indicating that deb its and credits are equal for the hundreds or thousands of transactions en tered in the ledger. While the trial balance provides arithmetic proof of the accuracy of the records, it does not provide theoretical proof. For ex ample, if the purchase of equipment was incorrectly charged to Expense, the trial balance columns may agree, but theoretically the accounts would be wrong, as Expense would be overstated and Equipment understated. In addition to providing proof of arithmetic accuracy in accounts, the tri al balance facilitates the preparation of the periodic nancial statements. Generally, the trial balance comprises the rst two columns of a work sheet, from which nancial statements are prepared. The worksheet pro cedure is discussed in 8.
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Move capacitor CS from its parallel connection across RS2 to a position across RS1 in Fig. 4-33. Let RG 1 M ; RS1 800 ; RS2 1:2 k ; and RL 1 k . The JFET is characterized by gm 0:002 S and rds 30 k . Find (a) the voltage-gain ratio Av vL =vi ; b the currentgain ratio Ai iL =ii ; c the input impedance Rin , and (d) the output impedance Ro .
in Problem 30.12(a, ii).]
By KVL, 1
iL + LL _
Divide the interval [0, 1] into n equal parts, as indicated in Fig. 30-8, making each [(i 1)/n, i/n], let xi be the right endpoint i/n. Then (30.1) becomes
Fig. 7-18 Using vi and vL as node voltages, we have vi vL RG 1 1 1 1 1 1 1 1 Req rds RS2 RL 30 103 1:2 103 1 103 536 ii 2
By KCL and Ohm s law, vL ii gm vgs Req Substitution of (1) and (2) into (3) and rearrangement lead to Av gm RG 1 Req vL 0:002 1 106 1 536 0:517 vi RG gm RG 1 Req 1 106 0:002 1 106 1 536 3
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Summary
Fig. 30-8
CHAP. 7]
(b) The current-gain ratio follows from part a as Ai iL vL =RL Av RG 0:517 1 106 1070:4 ii vi vL =RG 1 Av RL 1 0:517 1 103 ii vi vL vi 1 Av RG RG (4)
We can make the subdivision ner and ner by letting n approach in nity. Then,
vi RG 1 106 2:07 M ii 1 Av 1 0:517
(d) We remove RL and connect a driving-point source oriented such that vdp vL . With vi deactivated (shorted), vgs vdp . Then, by KCL, 1 1 1 1 1 1 idp vdp gm gm vgs vdp RS2 rds RG RS2 rds RG vdp 1 1 and 348:7 Ro 1 1 1 1 1 1 idp gm 0:002 3 3 6 RS2 rds RG 1:2 10 30 10 1 10
n 6
Use the small-signal equivalent circuit to predict the peak values of id and vds in Example 4.3. Compare your results with that of Example 4.3, and comment on any di erences.
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