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(a) Apply the results of Section 8.6 to the small-signal equivalent circuit of Fig. 8-11 to determine the Miller admittance. (b) Utilizing the Miller admittance, draw the high-frequency small-signal equivalent circuit and determine the voltage-gain ratio.

(a) With load resistor RL and feedback capacitor Cgd removed from the circuit of Fig. 8-11, the forward gain KF follows from an application of Ohm s law: KF VL gm rds kRD s rds kRD Cds 1 Vgs gm rds kRD s Cgd s rds kRD Cds 1 1

1 dx f (x)

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In the frequency range of interest and for typical values of rds ; RD ; and Cds , generally js rds kRD Cds j ( 1; thus, the Miller admittance can be synthesized as a capacitor with value CM YM 1 gm rds kRD Cgd s 3 Hence, the 4

2,000

(b) Since there is no feedback of output voltage to the input network of Fig. 8-11, KR 0. output admittance, as suggested by (8.48), is simply 1 KR YF YF sCgd

In each case, we employ the chain rule to show that the derivative of the function on the right is the integrand on the left. (a) Dx x 1 tan 1 a a x 1 1 1 Dx tan 1 = a a a1+ x 2 a 1 1 1 = 2 = 2 a 1 + x2 a + x2 =

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The equivalent circuit of Fig. 8-11 can be converted to the form of Fig. 8-12(b), as displayed in Fig. 8-26. By Ohm s law, VL gm Vgs s Cds Cgd gds GD GL 5

Since Vgs Vi , the required voltage-gain ratio follows as Av s VL gm Vi s Cds Cgd gds GD GL (See Problem 8.25.) 6

1 a 1 a2 [a > 0 implies a = [ u v = uv] 1

RG _

+ LL _

a2 ]

The same amount is used whether or not there is a balance in the Allowance for Bad Debt account. However, if any substantial balance should accumulate in the allowance account, a change in the percentage gure would become appropriate.

Fig. 8-26

CHAP. 8]

1 a2

The high-frequency equivalent circuit for the CS JFET ampli er of Fig. 4-5 is given by Fig. 8-11. Let RG 1 M ; RL RD 2 k ; rds 50 k ; gm 0:016 S; Cgs 3 pF; Cds 1 pF; and Cgd 2:7 pF. By SPICE methods, determine the voltage gain for a 50 MHz impressed signal.

The netlist code below describes the circuit:

CHAP. 37]

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Prb8_20.CIR vi 1 0 AC 0.25V RG 1 0 1Megohm Cgs 1 0 3pF Cgd 1 2 2.7pF Ggm 2 0 (1,0) 0.016 rds 2 0 50kohm Cds 2 0 1pF RD 2 0 2kohm RL 2 0 2kohm .AC DEC 100 1MegHz 100MegHz .PROBE .END

Balance Sheet Method Under the balance sheet method, every account is aged ; that is, each item in the balance is related to the sale date. The further past due the ac count, the more probable it is that the customer is unwilling or unable to pay. A typical analysis is shown below. Age of Account A/R Balance 1 30 days $ 8,000 31 60 days 12,000 61 90 days 6,000 91 180 days 3,000 Over 180 days 920 $29,920 Est. % Uncollectible Amount 1% $ 80 3% 360 5% 300 20% 600 460 50% $1,800

Execute hPrb8_20.CIRi and use the Probe feature of PSpice to give Fig. 8-27. From the marked points, it is seen that the voltage gain at 50 MHz is Av 10:36 128:28

Fig. 8-27

(a) By Problem 37.8(a), with a = 2,

For the CG JFET ampli er of Fig. 4-28, let VDD 15 V, R1 R2 10 k , RD 500 , RS 2 k , and CC1 CC2 15 F. Add a load resistor RL 15 k . The JFET is modeled by the parameters of Problem 4.4. Use SPICE methods to implement a wide frequency range study to determine low- and high-frequency cuto points for this ampli er.

Fig. 9-26

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